Transistor scaling has provided ever-increasing transistor performance and density for the past few decades. For example, scaling of a gate length of a transistor, also known as a channel length of a planar transistor, not only decreases a size of the transistor, but also enhances its on-state current. However, with the decrease of the channel length, short channel effects (SCEs) that significantly increases an off-state current of the transistor become a bottle neck for advancement of scaling of the channel length. Other techniques, such as the use of a high mobility channel, a channel region formed of a material with a mobility higher than that of silicon, and applying strain to the channel region are considered to further the progress of performance enhancement. Recently, non-planar transistors such as FinFET and nanowire FET are shown to be promising in reducing the off-state current by limiting a body thickness of the transistor, thereby breaking through the bottle neck that hinders the scaling roadmap. Many of performance enhancement techniques for planar transistors such as the use of the high mobility channel are being considered to be applied to the non-planar transistors.